Phase lock loops utilize a phase detector for comparing the phase of a reference clock with that of an output clock that utilizes a voltage controlled oscillator (VCO) to generate a phase error that varies the control voltage on the input to the VCO. By adjusting this voltage, the phase of the VCO can be locked the phase of the reference clock. Typically, some type of loop filter is disposed between the phase detector and the VCO. In a charge pump PLL, a typical phase detector generates control voltages for controlling a charge pump circuit which is operable to selectively pump charge to a node for increasing a voltage level or pulling charge from the node to provide a decreasing voltage level. To increase the voltage level, charge is sourced from a supply voltage and, to decrease the voltage level, charge is sinked to a ground reference. When the relative phase between the VCO and the reference clock are either lagging or leading, then either the sourcing or sinking of a charge pump is controlled.
This charge pump is typically facilitated with two current sources that are switched to the voltage input to the VCO. When charge is being sourced to the node, the phase of the VCO will change from either a lagging or leading to a leading or lagging phase, such that the phase detector will then cause the charge pump to sink current. When the PLL is locked, the phase error should be substantially at a zero phase error which should result in no current being sourced to or sinked from the voltage control input of the VCO. However, conventional charge pumps are fabricated with two transistor switches, one for sourcing current and one for sinking current, that are switched to either a conducting state or a non-conducting state. However, the current source is a function of the voltage on the VCO input. As the voltage changes, the characteristics of the switch and the associated current source will also change. Therefore, if the voltage changes, i.e., it is not constant, there is a possibility that the currents will not be balanced. If they are not balanced, then a phase error can result at phase lock, which could cause jitter in the clock. Thus, it is desirable that the currents are balanced for all possible voltages input to the VCO over the entire range required during the operation thereof.